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74HC259; 74HCT259
8-bit addressable latch
Rev. 04 -- 25 February 2009 Product data sheet
1. General description
The 74HC259; 74HCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7-A. The 74HC259; 74HCT259 are high-speed 8-bit addressable latches designed for general purpose storage applications in digital systems. They are multifunctional devices capable of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0 to Q7). They also incorporates an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The 74HC259; 74HCT259 has four modes of operation:
* Addressable latch mode, in this mode data on the data line (D) is written into the
addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states.
* Memory mode, in this mode all latches remain in their previous states and are
unaffected by the data or address inputs.
* Demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows
the state of the data input (D) with all other outputs in the LOW state.
* Reset mode, in this mode all outputs are LOW and unaffected by the address inputs
(A0 to A2) and data input (D). When operating the 74HC259; 74HCT259 as an address latch, changing more than one address bit could impose a transient wrong address. Therefore, this should only be done while in the Memory mode.
2. Features
I I I I I I I I Combined demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random (addressable) data entry Easily expandable Common reset input Useful as a 3-to-8 active HIGH decoder Input levels: N For 74HC259: CMOS level N For 74HCT259: TTL level
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from -40 C to +85 C and from -40 C to +125 C
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74HC259N 74HCT259N 74HC259D 74HCT259D 74HC259DB 74HCT259DB 74HC259PW 74HCT259PW 74HC259BQ 74HCT259BQ -40 C to +125 C DHVQFN16 -40 C to +125 C TSSOP16 -40 C to +125 C SSOP16 -40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT109-1 SOT338-1 SOT403-1 -40 C to +125 C DIP16 Description plastic dual in-line package; 16 leads (300 mil) Version SOT38-4 Type number
plastic dual in-line compatible thermal enhanced very SOT763-1 thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm
4. Functional diagram
13 15 14
Z9 G8 G10 9,10D 0 1 C10 8R
DX 14 LE Q0 13 D Q1 Q2 Q3 1 2 3 A0 A1 A2 MR 15
mna573
4
1 4 5 6 7 9 10 11 12 2 3
0 G 2 0 7 1
5 6 2 7 3 9 4 10 5 11 6 12 7
mna572
Q4 Q5 Q6 Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
2 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
Q0 1 2 3 A0 A1 A2 1-of-8 DECODER 8 LATCHES 14 15 13 LE MR D Q1 Q2 Q3 Q4
4 5 6 7 9
Q5 10 Q6 11 Q7 12
mna571
Fig 3.
Functional diagram
5. Pinning information
5.1 Pinning
74HC259 74HCT259
terminal 1 index area A1 16 VCC 15 MR 14 LE 13 D 12 Q7 11 Q6 10 Q5 9
001aaj444
74HC259 74HCT259
A0 A1 A2 Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8
2 3 4 5 6 7 8 GND Q4 9 GND(1)
16 VCC 15 MR 14 LE 13 D 12 Q7 11 Q6 10 Q5
A2 Q0 Q1 Q2 Q3
1
A0
Q4
001aaj445
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input.
Fig 4.
Pin configuration (DIP16, SO16, SSOP16 and TSSOP16)
Fig 5.
Pin configuration (DHVQFN16)
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
3 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
5.2 Pin description
Table 2. Symbol A0, A1, A2 GND D LE MR VCC Pin description Pin 1, 2, 3 8 13 14 15 16 Description address input ground (0 V) data input latch enable input (active LOW) conditional reset input (active LOW) supply voltage
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
6. Functional description
Table 3. Function table[1] Input MR Reset (clear) L Demultiplexer L (active HIGH 8-channel) L decoder (when D = H) L L L L L L Memory (no action) Addressable latch H H H H H H H H H
[1]
Operating mode
Output LE H L L L L L L L L H L L L L L L L L D X d d d d d d d d X d d d d d d d d A0 X L H L H L H L H X L H L H L H L H A1 X L L H H L L H H X L L H H L L H H A2 X L L L L H H H H X L L L L H H H H Q0 L L L L L L L L q0 q0 q0 q0 q0 q0 q0 q0 Q1 L Q2 L L Q3 L L L Q4 L L L L Q5 L L L L L Q6 L L L L L L Q7 L L L L L L L Q=d q7 q7 q7 q7 q7 q7 q7 Q=d
Q=d L L L L L L L q1
Q=d L L L L L L q2 q2
Q=d L L L L L q3 q3 q3
Q=d L L L L q4 q4 q4 q4
Q=d L L L q5 q5 q5 q5 q5
Q=d L L q6 q6 q6 q6 q6 q6
Q=d L
Q = d q1 q1 q1 q1 q1 q1 q1
Q = d q2 q2 q2 q2 q2 q2
Q = d q3 q3 q3 q3 q3
Q = d q4 q4 q4 q4
Q = d q5 q5 q5
Q = d q6 q6
Q = d q7
H = HIGH voltage level; L = LOW voltage level; X = don't care; d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
4 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
Table 4. LE L H L H
[1]
Operating mode select table[1] MR H H L L Mode Addressable latch mode Memory mode Demultiplexer mode Reset mode
H = HIGH voltage level; L = LOW voltage level.
7. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb = -40 C to +125 C DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package
[1] [2] [3] [4] [5]
[2] [3] [4] [5]
Conditions VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V VO = -0.5 V to VCC + 0.5 V
[1] [1]
Min -0.5 -70 -65 -
Max +7.0 20 20 25 +70 +150 750 500 500 500
Unit V mA mA mA mA mA C mW mW mW mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 C. Ptot derates linearly with 8 mW/K above 70 C. Ptot derates linearly with 5.5 mW/K above 60 C. Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
5 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
8. Recommended operating conditions
Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb t/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions 74HC259 Min 2.0 0 0 -40 Typ 5.0 1.67 Max 6.0 VCC VCC +125 625 139 83 74HCT259 Min 4.5 0 0 -40 Typ 5.0 1.67 Max 5.5 VCC VCC +125 139 V V V C ns/V ns/V ns/V Unit
9. Static characteristics
Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC259 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4.0 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC input leakage current supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0 0 0 0.15 0.16 0.1 0.1 0.1 0.26 0.26 0.1 8.0 0.1 0.1 0.1 0.33 0.33 1 80 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V A A 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions Min 25 C Typ Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
6 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI input capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL; VCC = 4.5 V IO = -20 A IO = -4.0 mA VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pin An, LE pin D pin MR CI input capacitance 150 120 75 3.5 540 432 270 675 540 338 735 588 368 A A A pF 0 0.15 0.1 0.26 0.1 8.0 0.1 0.33 1 80 0.1 0.4 1 160 V V A A 4.4 3.98 4.5 4.32 4.4 3.84 4.4 3.7 V V Conditions Min 25 C Typ 3.5 Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max pF
74HCT259 VIH VIL VOH 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
7 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
10. Dynamic characteristics
Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter 74HC259 tpd propagation delay D to Qn; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V An to Qn; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V LE to Qn; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tPHL HIGH to LOW propagation delay MR to Qn; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tt transition time see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width LE HIGH or LOW; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR LOW; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 70 14 12 17 6 5 90 18 15 105 21 18 ns ns ns 70 14 12 17 6 5 90 18 15 105 21 18 ns ns ns
[3] [2] [2] [2]
Conditions Min
25 C Typ[1] Max
-40 C to +85 C -40 C to +125 C Unit Min Max Min Max
-
58 21 18 17 58 21 17 17 55 20 17 16 50 18 15 14 19 7 6
185 37 31 185 37 31 170 34 29 155 31 26 75 15 13
-
230 46 39 230 46 39 215 43 37 195 39 33 95 19 16
-
280 56 48 280 56 48 255 51 43 235 47 40 119 22 19
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
8 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter tsu set-up time Conditions Min D, An to LE; see Figure 10 and Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time D to LE; see Figure 10 and Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V An to LE; see Figure 10 and Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance propagation delay fi = 1 MHz; VI = GND to VCC
[4]
25 C Typ[1] Max
-40 C to +85 C -40 C to +125 C Unit Min Max Min Max
80 16 14
19 7 6
-
100 20 17
-
120 24 20
-
ns ns ns
0 0 0
-19 -6 -5
-
0 0 0
-
0 0 0
-
ns ns ns
2 2 2 -
-11 -4 -3 19
-
2 2 2 -
-
2 2 2 -
-
ns ns ns pF
74HCT259 tpd D to Qn; see Figure 6 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF An to Qn; see Figure 7 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF LE to Qn; see Figure 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tPHL HIGH to LOW propagation delay transition time pulse width MR to Qn; see Figure 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF see Figure 8 VCC = 4.5 V tW LE HIGH or LOW; see Figure 8 VCC = 4.5 V MR LOW; see Figure 9 VCC = 4.5 V tsu set-up time D, An to LE; see Figure 10 and Figure 11 VCC = 4.5 V
74HC_HCT259_4
[2]
[2]
23 20 25 20 22 20 23 20 7
39 41 38 39 15
-
49 51
-
59 62
ns ns ns ns ns ns ns ns ns
[2]
-
48 49 19
-
57 59 22
[3]
tt
-
19 18
11 10
-
24 23
-
29 27
-
ns ns
17
10
-
21
-
26
-
ns
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
9 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
Table 8. Dynamic characteristics ...continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12. Symbol Parameter th hold time Conditions Min D to LE; see Figure 10 and Figure 11 VCC = 4.5 V An to LE; see Figure 10 and Figure 11 VCC = 4.5 V CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC - 1.5 V
[4]
25 C Typ[1] Max
-40 C to +85 C -40 C to +125 C Unit Min Max Min Max
0
-8
-
0
-
0
-
ns
0 -
-4 19
-
0 -
-
0 -
-
ns pF
[1] [2] [3] [4]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs.
11. Waveforms
VCC D input GND tPHL VOH Qn output VOL VM
001aah123
VM
tPLH
Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Data input to output propagation delays
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
10 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
VCC An input GND tPHL VOH Qn output VOL VM
001aah122
VM
tPLH
Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Address input to output propagation delays
VCC D input GND
VCC LE input GND tW tPHL VOH Qn output VOL VY VM VX tTHL tTLH
001aaj446
VM
tPLH
Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8.
Enable input to output propagation delays and pulse width
VCC MR input GND tW tPHL VOH Qn output VOL VM
001aah124
VM
Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
Master reset input to output propagation delays
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
11 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
VCC LE input GND VM
tsu
VCC D input GND VM
tsu th th
VOH Qn output VOL
001aah125
Q=D
VM
Q=D
Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. Data input to latch enable input set-up and hold times
VCC
An input
GND
VM
ADDRESS STABLE
tsu
VCC
th
LE input
GND
VM
001aah126
Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 11. Address input to latch enable input set-up and hold times Table 9. Type 74HC259 74HCT259 Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V VX 0.1VCC 0.1VCC VY 0.9VCC 0.9VCC
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
12 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VCC
VCC
G
VI
VO
RL
S1
DUT
RT CL
open
001aad983
Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch
Fig 12. Load circuit for measuring switching times Table 10. Type 74HC259 74HCT259 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
13 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 b2 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 95-01-14 03-02-13
Fig 13. Package outline SOT38-4 (DIP16)
74HC_HCT259_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
14 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 pin 1 index Lp 1 e bp 8 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT109-1 (SO16)
74HC_HCT259_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
15 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 A1 pin 1 index Lp L 1 bp 8 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 15. Package outline SOT338-1 (SSOP16)
74HC_HCT259_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
16 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 16. Package outline SOT403-1 (TSSOP16)
74HC_HCT259_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
17 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 7 vMCAB wM C y1 C
C y
1 Eh 16
8 e 9
15 Dh
10 X 2.5 scale 5 mm
0
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 17. Package outline SOT763-1 (DHVQFN16)
74HC_HCT259_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
18 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
13. Abbreviations
Table 11. Acronym CDM CMOS DUT ESD HBM LSTTL MM TTL Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic
14. Revision history
Table 12. Revision history Release date 20090225 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT259_3 Document ID 74HC_HCT259_4 Modifications: 74HC_HCT259_3 74HC_HCT259_CNV_2
* *
Added type number 74HC259N and 74HCT259N (DIP16 package) Added type number 74HC259DB and 74HCT259DB (SSOP16 package) Product data sheet Product specification 74HC_HCT259_CNV_2 -
20090108 19970828
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
19 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT259_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 25 February 2009
20 of 21
NXP Semiconductors
74HC259; 74HCT259
8-bit addressable latch
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 February 2009 Document identifier: 74HC_HCT259_4

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